Bit-Matrix Decomposition and Dynamic Reconfiguration: A Unified Arithmetic Processor Architecture, Design and Test

Macrocell also based on a multiply/add approach [2]. Abstract This paper presents the architecture, design and Other researchers, including Hwang (refer to Section test of a unified arithmetic processor, developed based on 6.8 of [21]), Swartzlander [18] and Parhami [16], have recently proposed partial product bit-matrix introduced general (or universal) arithmetic architectures decomposition and dynamic reconfiguration parallel which utilize an array of small multipliers to construct any processing mechanism. size multipliers in a static (not reconfigurable) way. Since By trading bitwidth for array size, the processor is able the scheme (see [21]) uses 4x4 multipliers for all levels of to perform several operations involving the the bit reduction, and those small multipliers are connected multiplication of two 32-b numbers and two 4x4 in parallel-sequential, it works only for multiplications, matrices of 8-b numbers, as well as the evaluation of the the speed is limited as well as. In contrast, our scheme uses inner product of two size-4 arrays of 16-b numbers. All small multipliers only in the first level of bit reduction, and of them are important to many applications including uses fast adders in the remaining two levels fully in graphics and volume rendering. parallel, which allows easy reconfiguration and higher A set of very simple and efficient reconfigurable speed. Recently Marshall et al have proposed a general switches is utilized to achieve the high performance. Only reconfigurable arithmetic unit using FPGAs [15], which is two extra bits are needed for all reconfiguration controls. flexible enough for many basic arithmetic operations, but The architecture also possesses a superiority for high it is significantly slower than the one proposed in this